The present invention claims the benefit of Korean Patent Application No. P 2000-0076006 filed in Korea on Dec. 13, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a display device, and more particularly, to a liquid crystal display (LCD) panel of high resolution and a method for manufacturing the same.
2. Discussion of the Related Art
Rapid developments in the field of information communication have caused an increase in the demand for thin, lightweight and low cost display devices for viewing information. Industries that develop display devices (or, simply, displays) are responding to these needs by placing high emphasis on developing flat panel-type displays. Historically, the Cathode Ray Tube (CRT) has been widely used as a display device for televisions, computer monitors and the like, because CRT screens can display various colors having high brightness. However, the CRT cannot adequately satisfy present demands for display applications that require display devices with reduced volume and weight, portability, lower power consumption, large screen size, and high resolution. Because of such requirements, the display industry has started placing more emphasis on developing flat panel displays to replace the CRT. Over the years, flat panel displays have found wide use in monitors manufactured for computers, spacecraft, aircraft, etc.
Some examples of the types of flat panel displays currently in use include the liquid crystal display (LCD), the electroluminescent display (ELD), the field emission display (FED), and the plasma display panel (PDP). Some characteristics that are required of an ideal flat panel display include light weight, high luminance, high efficiency, high resolution, high speed response time, low driving voltage, low power consumption, low cost, and natural color reproduction.
Generally, a phosphor material on a surface of the CRT emits light based on an externally applied display timing signal and an externally applied data signal, which control the trace of an electron beam. On the other hand, in an LCD panel, the electric field applied to the liquid crystals is controlled so as to control each crystal""s transmittivity of light.
Development and applications of thin film transistor (TFT)-based LCD displays having increased dimensions and increased resolution is in demand. To increase productivity during manufacture of such displays, it is desirable to continue efforts to simplify manufacturing process steps and to improve the yield.
It is noted that the pitch between two pads in an LCD panel is a parameter that can be optimized for realizing an LCD panel with high resolution. In other words, the realization of an LCD panel with high resolution depends on how much the pitch between two pads is decreased.
Some relevant constructional details of a related art LCD panel are explained hereinbelow with reference to FIGS. 1-3. FIG. 1 is a plane view illustrating architectural details of a related art LCD panel, and FIG. 2 is a sectional view of the LCD panel in FIG. 1 taken along line of I-Ixe2x80x2 in FIG. 1. Referring to FIG. 1 and FIG. 2, the related art LCD panel includes two glass substrates divided into a cell region (C), a pad region (P), and a liquid crystal interposed between them. A plurality of gate lines G1, G2 . . . Gn are arranged to cross a plurality of data lines D1, D2 . . . Dn on a first glass substrate 1 in the cell region (C), thereby defining a plurality of pixel regions in a matrix form. A pixel electrode 3 is formed in each pixel region. A TFT (Thin Film Transistor) is formed at each crossing point between a gate line and a data line.
The pad region P includes a plurality of gate pads Gp1, Gp2 . . . , Gpn and a plurality of data pads Dp1, Dp2 . . . Dpn. The gate pads transmit a gate signal output from a gate driving circuit (not shown) to the gate lines G1, G2 . . . Gn; and the data pads transmit a data signal output from a data driving circuit (not shown) to the data lines D1, D2 . . . Dn.
Although not shown in FIGS. 1 and 2, a black matrix layer and a color filter layer for displaying colors R, G, and B are arranged on a second glass substrate of the cell region. The black matrix layer prevents light from being transmitted from a pixel electrode and a TFT. A common electrode is arranged above the color filter layer so as to apply a common voltage to each pixel electrode 3.
The data pads are now explained with reference to FIG. 2. As shown in FIG. 2, the data pads Dp1, Dp2, and Dp3 extend from respective data lines D1, D2, and D3 in the cell region C. The data pads Dp1, Dp2 and Dp3 are formed above the gate insulating film 2 on the first substrate 1 in the pad region P with a fixed distance between two of them. Thereafter, a transparent conductive film 6 electrically connected to each data pad Dp1, Dp2, and Dp3 through a passivation film 4 on the data pads Dp1, Dp2, and Dp3 is formed. The transparent conductive film 6 transmits a driving signal received from an external driving circuit (not shown) through TCP (Tape Carrier Package) or COF (Chip on Film) to each data line.
The distance between each data line D1, D2, and D3 is called a xe2x80x9cpitch.xe2x80x9d For example, in FIGS. 1 and 2, the pitch Pxe2x80x2 is a distance from the center of line D1 to that of line D2. In a related art LCD panel, the pitch Pxe2x80x2 is about 50 xcexcm and the respective transparent conductive films 6 require a minimum distance xe2x80x9cWxe2x80x9d to be connected to a Tape Carrier Package (TCP), which electrically connects the transparent conductive films 6 to a driving circuit.
However, to obtain an LCD panel of high resolution, that is, an LCD panel with more than 200 Pixels Per Inch (PPI), the pitch Pxe2x80x2 should be less than 50 xcexcm (e.g., approximately 42 xcexcm). Accordingly, with the configuration illustrated in FIGS. 1 and 2, an LCD panel of resolution more than 200 PPI may not be obtained.
Many methods to obtain a higher pitch among adjacent data pads are proposed. For example, a Double Bank structure separately arranges pads at both sides of an LCD panel. FIG. 3 is a plane view illustrating a related art LCD panel with double bank structure. In FIG. 3, the odd numbered data pads such as Dp1, Dp3, . . . , Dpnxe2x88x921 are arranged at a lower portion (or at an upper portion) of an LCD panel and the even numbered data pads such as Dp2, Dp4 . . . , Dpn are arranged at an upper portion (or a lower portion) of the panel, thereby obtaining a pitch that is higher than that obtained with the Single Bank structure shown in FIG. 1. In the cell region of first substrate 1 in FIG. 3, a plurality of gate lines G1, G2 . . . Gn are formed to cross a plurality of data lines D1, D2 . . . Dn. Also, in the pad region of the substrate 1, data pads Dp1, Dp2, Dp3 . . . , Dpnxe2x88x921, and Dpn on corresponding data lines are alternately arranged at an upper or a lower portion of the LCD panel as shown in FIG. 3.
However, a related art LCD panel has the following problems. First, the Single Bank structure (such as that shown in FIG. 1) can not obtain an LCD panel having a resolution more than 200 PPI, because a Single Bank structure places a limit on decreasing the pitch, which is a distance between adjacent data pads, since a minimum pad width is required for electrical contact with a driving circuit. Second, although the minimum width required for electrical contact with the driving circuit is obtained in the Double Bank structure in spite of a decreased pitch, a separate arrangement of data pads on both sides of the LCD panel is required. Such a Double Bank architecture thus complicates the module fabrication process and driving circuitry arrangement. Furthermore, the double bank structure makes fabrication of compact panels impossible and also increases the LCD panel production cost.
Accordingly, the present invention is directed to an LCD panel and a method for manufacturing the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an LCD panel of a large area and a method for manufacturing the same, in which a pixel pitch is decreased, and thus an LCD of a high resolution can be obtained.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve the objects and other advantages in accordance with the purpose of the invention, as embodied and broadly described herein, an LCD panel according to one embodiment of the present invention includes an insulating substrate defined as a cell region and a pad region; a plurality of gate lines crossing a plurality of data lines, thereby defining a plurality of pixel regions on the cell region; a first set of data pads formed in the pad region and extending from the odd numbered data lines; and a second set of data pads formed in the pad region in a single-bank structure with the first set of data pads. Each data pad in the second set of data pads is electrically connected to a corresponding even numbered data line and arranged in a direction parallel to that of the first set of data pads. Furthermore, each data pad in the second set of data pads is placed in the pad region at a location whose longitudinal axis is collinear with that of an adjacent odd numbered data line.
In another embodiment, the present invention contemplates a method of manufacturing an LCD panel. The method includes forming a plurality of gate lines in a cell region of a substrate and forming a plurality of conductive patterns on the substrate, wherein each conductive pattern has a first end in the cell region and a second end in the pad region; forming a gate insulating film on the substrate covering the plurality of gate lines and the plurality of conductive patterns; forming odd-numbered and even-numbered data lines in the cell region on the gate insulating film, wherein the longitudinal axis of each of the odd-numbered data lines is collinear with the second end of an adjacent one of the plurality of conductive patterns on the substrate; forming a first set of data pads in the pad region extending from the odd-numbered data lines on the gate insulating film above the plurality of conductive patterns; and forming a second set of data pads in the pad region in a single-bank structure with the first set of data pads, wherein each data pad in the second set of data pads is connected at least to the second end of a corresponding one of the plurality of conductive patterns and is arranged in a direction parallel to that of the first set of data pads.
In an LCD panel of the present invention, conductive patterns are connected to the even numbered data lines at the time of patterning the gate lines. These conductive patterns may also be formed of the same material as that of the gate lines and in the same process as that used to form the gate lines. Thereafter, a gate insulating layer, data lines, and a passivation film are formed sequentially. Then, a semiconductor layer which is to be used as a channel of a thin film transistor is formed. The source and drain electrodes are also formed at the time of forming the data lines.
The passivation film and the gate insulating film may be patterned at the same time. Then, appropriate contact holes are formed to expose an end part (in the pad region) of the odd numbered data lines, an end part (in the cell region) of the conductive patterns, an end part of even numbered data lines adjacent to the end part of the conductive patterns in the cell region, and an opposite end part (in the pad region) of the conductive patterns. Subsequently pixel electrodes are formed in pixel regions, and a transparent conductive film connected to the odd numbered data lines is formed through corresponding contact hole to form the first data pads (i.e., the odd-numbered data pads). At the same time, a transparent conductive film which connects the end part of the conductive patterns to the end part of adjacent even numbered data lines is formed. Also, a transparent conductive film connected to the opposite end part of the conductive patterns is formed, thereby forming the second data pads (i.e., the even-numbered data pads).
As per one embodiment of the present invention, the even numbered data lines are formed only up to the cell region and then extended up to the pad region using the conductive patterns. The conductive pattern extensions of the even numbered data lines pass through a lower portion of the first data pads. On the other hand, in another embodiment of the present invention, the conductive patterns are placed on one side of the first data pads and no portion of the conductive patterns is placed perpendicularly below the first set of data pads. These conductive patterns may be formed with gate lines, and refracted appropriately so that the even numbered data pads could be extended from the even numbered data lines and arranged parallel to the odd-numbered data pads along the longitudinal direction of odd-numbered data lines.
In another embodiment of the present invention, the conductive patterns are not formed, but, instead, the even numbered data lines are made longer than the odd numbered data lines in the pad region of the substrate. The even numbered data lines may be refracted appropriately to arrange the even numbered data pads in parallel to the odd numbered data pads along the longitudinal direction of the odd numbered data lines. Therefore, the first and second sets of data pads are arranged not adjacent but alternately up and down on a plane.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.